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  +-------------------------------------------------------------------------
  |
  |      6510 CPU ILLEGAL INSTRUCTION SET
  |
  +-------------------------------------------------------------------------
  |
  |  Related topics:
  |
  |   <A HREF="BMAIN.HTM">6510 instruction set</A>
  |   <A HREF="BCHRT651.HTM">6510 instruction chart</A>
  |
  |   <A HREF="EBMAIN.HTM">65816 extended instruction set</A>
  |   <A HREF="BCHRT816.HTM">65816 instruction chart</A>
  |
  |   <A HREF="ADDRIDX.HTM">6510/65816 Addressing modes</A>
  |
  |  Instructions set:
  |
  |     <A HREF="BANC.HTM">ANC</A>   AND #immediate, copy accu-bit 7 to carry
  |     <A HREF="BANE.HTM">ANE</A>   <B>Instable!</B>
  |     <A HREF="BARR.HTM">ARR</A>   AND #immediate, ROR accu
  |     <A HREF="BASR.HTM">ASR</A>   AND #immediate, LSR accu
  |
  |     <A HREF="BDCP.HTM">DCP</A>   DEC memory, CMP memory
  |
  |     <A HREF="BISB.HTM">ISB</A>   INC memory, SBC memory
  |
  |     <A HREF="BJAM.HTM">JAM</A>   Locks up machine
  |
  |     <A HREF="BLAE.HTM">LAE</A>   <B>Instable!</B>
  |     <A HREF="BLAX.HTM">LAX</A>   LDA memory, TAX
  |     <A HREF="BLXA.HTM">LXA</A>   <B>Instable!</B>
  |
  |     <A HREF="BNOP.HTM">NOP</A>   No operation
  |
  |     <A HREF="BRLA.HTM">RLA</A>   ROL memory, AND memory
  |     <A HREF="BRRA.HTM">RRA</A>   ROR memory, ADC memory
  |
  |     <A HREF="BSAX.HTM">SAX</A>   Accu AND X-Register into memory
  |     <A HREF="BSBC.HTM">SBC</A>   Subtract memory from accumulator with borrow
  |     <A HREF="BSBX.HTM">SBX</A>   Accu AND X-Register, subtract operand, result into X-Register
  |     <A HREF="BSHA.HTM">SHA</A>   <B>Instable!</B>
  |     <A HREF="BSHS.HTM">SHS</A>   <B>Instable!</B>
  |     <A HREF="BSHX.HTM">SHX</A>   <B>Instable!</B>
  |     <A HREF="BSHY.HTM">SHY</A>   <B>Instable!</B>
  |     <A HREF="BSLO.HTM">SLO</A>   ASL memory, ORA memory
  |     <A HREF="BSRE.HTM">SRE</A>   LSR memory, EOR memory
  |
  +-------------------------------------------------------------------------

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